1. Field of the Invention
The invention is generally directed to in-system programming (ISP) of programmable logic devices (PLD's). The invention is more specifically directed to nonvolatile memory devices that support in-system reconfiguring of field-programmable gate array devices (FPGA's).
2a. Cross Reference to Related Patents
The disclosures of the following U.S. patent(s) are incorporated herein by reference:
(A) U.S. Pat. No. 5,212,652 issued May 18, 1993 to Om Agrawal et al, (filed as Ser. No. 07/394,221 on Aug. 15, 1989) and entitled, PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE;
(B) U.S. Pat. No. 5,621,650 issued Apr. 15, 1997 to Om Agrawal et al, and entitled, PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTERCONNECT BUSES;
(C) U.S. Pat. No. 5,077,691 issued Dec. 31, 1991 to Haddad et al, and entitled, FLASH EEPROM ARRAY WITH NEGATIVE GATE VOLTAGE ERASE OPERATION;
(D) U.S. Pat. No. 4,958,321 issued Sep. 18, 1990 to Chang; Chi and entitled, ONE TRANSISTOR FLASH EPROM CELL; and
(E) U.S. Pat. No. 5,617,357 issued Apr. 1, 1997 to Haddad et al, and entitled, FLASH EEPROM MEMORY WITH IMPROVED DISCHARGE SPEED USING SUBSTRATE BIAS AND METHOD THEREFOR.
2b. Cross Reference to Related Other Publications
The following publication(s) is/are believed to be related to the present application and is/are cited here for purposes of reference:
(a) Xilinx Data Manual pages 6-1:6-10 entitled "XC1700D Family of Serial Configuration PROMs" (Jun. 1, 1996).
3. Description of the Related Art
Field-Programmable Logic Devices (FPLD's) have continuously evolved to better serve the unique needs of different end-users. From the time of introduction of simple PLD's such as the Advanced Micro Devices 22V10.TM. Programmable Array Logic device (PAL), the art has branched out in several different directions and bloomed.
One evolutionary branch of FPLD's has grown along a paradigm known as Complex PLD's or CPLD's. This paradigm is characterized by devices such as the Advanced Micro Devices MACH.TM. family. Examples of CPLD circuitry are seen in U.S. Pat. No. 5,015,884 (issued May 14, 1991 to Om P. Agrawal et al.) and U.S. Pat. No. 5,151,623 (issued Sep. 29, 1992 to Om P. Agrawal et al.).
Another evolutionary chain in the art of field programmable logic has branched out along a paradigm known as Field Programmable Gate Arrays or FPGA's. Examples of such devices include the XC2000.TM. and XC3000.TM. families of FPGA devices introduced by Xilinx, Inc. of San Jose, Calif. The architectures of these devices are exemplified in U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is originally assigned to Xilinx, Inc.
An FPGA device can be characterized as an integrated circuit that has four major features as follows.
(1) A user-accessible, configuration-defining memory means, such as SRAM, PROM, EPROM, EEPROM, anti-fused, fused, or other, is provided in the FPGA device so as to be at least once-programmable by device users for defining user-provided configuration instructions. Static Random Access Memory or SRAM is of course, a form of reprogrammable memory that can be differently programmed many times. Electrically Erasable and reProgrammable ROM or EEPROM is an example of nonvolatile reprogrammable memory. The configuration-defining memory of an FPGA device can be formed of mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM) although this is not a popular approach.
(2) Input/Output Blocks (IOB's) are provided for interconnecting other internal circuit components of the FPGA device with external circuitry. The IOB's' may have fixed configurations or they may be configurable in accordance with user-provided configuration instructions stored in the configuration-defining memory means.
(3) Configurable Logic Blocks (CLB's) are provided for carrying out user-programmed logic functions as defined by user-provided configuration instructions stored in the configuration-defining memory means.
Typically, each of the many CLB's of an FPGA has at least one lookup table (LUT) that is user-configurable to define any desired truth table,--to the extent allowed by the address space of the LUT. Each CLB may have other resources such as LUT input signal pre-processing resources and LUT output signal post-processing resources. Although the term `CLB` was adopted by early pioneers of FPGA technology, it is not uncommon to see other names being given to the repeated portion of the FPGA that carries out user-programmed logic functions. The term, `LAB` is used for example in U.S. Pat. No. 5,260,611 to refer to a repeated unit having a 4-input LUT.
(4) An interconnect network is provided for carrying signal traffic within the FPGA device between various CLB's and/or between various IOB's and/or between various IOB's and CLB's. At least part of the interconnect network is typically configurable so as to allow for programmably-defined routing of signals between various CLB's and/or IOB's in accordance with user-defined routing instructions stored in the configuration-defining memory means.
In some instances, FPGA devices may additionally include embedded volatile memory for serving as scratchpad memory for the CLB's or as FIFO or LIFO circuitry. The embedded volatile memory may be fairly sizable and can have 1 million or more storage bits in addition to the storage bits of the device's configuration memory.
Modern FPGA's tend to be fairly complex. They typically offer a large spectrum of user-configurable options with respect to how each of many CLB's should be configured, how each of many interconnect resources should be configured, and/or how each of many IOB's should be configured. This means that there can be thousands or millions of configurable bits that may need to be individually set or cleared during configuration of each FPGA device.
Rather than determining with pencil and paper how each of the configurable resources of an FPGA device should be programmed, it is common practice to employ a computer and appropriate FPGA-configuring software to automatically generate the configuration instruction signals that will be supplied to, and that will ultimately cause an unprogrammed FPGA to implement a specific design. (The configuration instruction signals may also define an initial state for the implemented design, that is, initial set and reset states for embedded flip flops and/or embedded scratchpad memory cells.)
The number of logic bits that are used for defining the configuration instructions of a given FPGA device tends to be fairly large (e.g., 1 Megabits or more) and usually grows with the size and complexity of the target FPGA. Time spent in loading configuration instructions and verifying that the instructions have been correctly loaded can become significant, particularly when such loading is carried out in the field.
For many reasons, it is often desirable to have in-system reprogramming capabilities so that reconfiguration of FPGA's can be carried out in the field.
FPGA devices that have configuration memories of the reprogrammable kind are, at least in theory, `in-system programmable` (ISP). This means no more than that a possibility exists for changing the configuration instructions within the FPGA device while the FPGA device is `in-system` because the configuration memory is inherently reprogrammable. The term, `in-system` as used herein indicates that the FPGA device remains connected to an application-specific printed circuit board or to another form of end-use system during reprogramming. The end-use system is of course, one which contains the FPGA device and for which the FPGA device is to be at least once configured to operate within in accordance with predefined, end-use or `in the field` application specifications.
The possibility of reconfiguring such inherently reprogrammable FPGA's does not mean that configuration changes can always be made with any end-use system. Nor does it mean that, where in-system reprogramming is possible, that reconfiguration of the FPGA can be made in timely fashion or convenient fashion from the perspective of the end-use system or its users. (Users of the end-use system can be located either locally or remotely relative to the end-use system.)
Although there may be many instances in which it is desirable to alter a pre-existing configuration of an `in the field` FPGA (with the alteration commands coming either from a remote site or from the local site of the FPGA), there are certain practical considerations that may make such in-system reprogrammability of FPGA's more difficult than first apparent (that is, when conventional techniques for FPGA reconfiguration are followed).
A popular class of FPGA integrated circuits (IC's) relies on volatile memory technologies such as SRAM (static random access memory) for implementing on-chip configuration memory cells. The popularity of such volatile memory technologies is owed primarily to the inherent reprogrammability of the memory over a device lifetime that can include an essentially unlimited number of reprogramming cycles.
There is a price to be paid for these advantageous features, however. The price is the inherent volatility of the configuration data as stored in the FPGA device. Each time power to the FPGA device is shut off, the volatile configuration memory cells lose their configuration data. Other events may also cause corruption or loss of data from volatile memory cells within the FPGA device.
Some form of configuration restoration means is needed to restore the lost data when power is shut off and then re-applied to the FPGA or when another like event calls for configuration restoration (e.g., corruption of state data within scratchpad memory).
The configuration restoration means can take many forms. If the FPGA device resides in a relatively large system that has a magnetic or optical or opto-magnetic form of nonvolatile memory (e.g., a hard magnetic disk)--and the latency of powering up such a optical/magnetic device and/or of loading configuration instructions from such an optical/magnetic form of nonvolatile memory can be tolerated--then the optical/magnetic memory device can be used as a nonvolatile configuration restoration means that redundantly stores the configuration data and is used to reload the same into the system's FPGA device(s) during power-up operations (and/or other restoration cycles).
On the other hand, if the FPGA device(s) resides in a relatively small system that does not have such optical/magnetic devices, and/or if the latency of loading configuration memory data from such an optical/magnetic device is not tolerable, then a smaller and/or faster configuration restoration means may be called for.
Many end-use systems such as cable-TV set tops, satellite receiver boxes, and communications switching boxes are constrained by prespecified design limitations on physical size and/or power-up timing and/or security provisions and/or other provisions such that they cannot rely on magnetic or optical technologies (or on network/satellite downloads) for performing configuration restoration. Their designs instead call for a relatively small and fast acting, non-volatile memory device (such as a securely-packaged EPROM IC), for performing the configuration restoration function. The small/fast device is expected to satisfy application-specific criteria such as: (1) being securely retained within the end-use system; (2) being able to store FPGA configuration data during prolonged power outage periods; and (3) being able to quickly and automatically re-load the configuration instructions back into the volatile configuration memory (SRAM) of the FPGA device each time power is turned back on or another event calls for configuration restoration.
The term `CROP device` will be used herein to refer in a general way to this form of compact, nonvolatile, and fast-acting device that performs `Configuration-Restoring On Power-up` services for an associated FPGA device.
Unlike its supported, volatilely reprogrammable FPGA device, the corresponding CROP device is not volatile, and it is generally not `in-system programmable`. Instead, the CROP device is generally of a completely nonprogrammable type such as exemplified by mask-programmed ROM IC's or by once-only programmable, fuse-based PROM IC's. Examples of such CROP devices include a product family that the Xilinx company provides under the designation `Serial Configuration PROMs` and under the trade name, XC1700D.TM.. These serial CROP devices employ one-time programmable PROM (Programmable Read Only Memory) cells for storing configuration instructions in nonvolatile fashion.
It is to be noted as a slight digression here, that abbreviated terms such as `PROM` (which may stand for: once Programmable Read Only Memory), `EPROM` (which may stand for: Eraseable and Programmable Read Only Memory) and `EEPROM` or `E-squared PROM` (which may stand for: Electrically Erasable and reProgrammable Read Only Memory) bear historical connotations in the industry with respect to the physics employed therein for performing programming and erasure (if any) operations. Fair debate may take place as to what specifically each of these abbreviated terms means when found in a specific publication.
In the following description, `EPROM` shall be understood to refer to a nonvolatile form of integrated storage that relies on hot electron injection both for programming and erasure operations.
The term `integrated storage` as used herein implies storage circuitry that is monolithically included in an integrated circuit chip or at least manufactured using the fabrication techniques of integrated circuits. The term `integrated storage` excludes nonvolatile forms of storage such as magnetic disk, optical disk, and tape which rely on some form of mechanical motion for their operations.
Further in the following description, `EEPROM` or `E-squared PROM` shall be understood to refer to a nonvolatile form of integrated storage that relies on Fowler-Nordheim (FN) tunneling both for programming and erasure operations.
Additionally in the following description, `FLASH` shall be understood to refer to a nonvolatile form of integrated storage that relies on Fowler-Nordheim (FN) tunneling for erasure operations and on hot electron injection for programming operations.
To avoid confusion, the term `NE.sub.-- NVIS` (Not Electrically-erasable, NonVolatile Integrated Storage) will be used herein to refer more generally to integrated devices which may be electrically programmed at least once to store data nonvolatilely but which may not be electrically erased. Thus, once-only programmable, fuse-based PROM IC's, and even the many-times programmable, UV-erasable PROM IC's all fall under the definition of `NE.sub.-- NVIS` because, although they are electrically programmable, they are not electrically-erasable. Mask-programmed ROM IC's do not because they are not electrically programmable. FLASH devices also do not fall under the definition of `NE.sub.-- NVIS` because they are electrically-erasable.
The term `NP.sub.-- NVIS` (Not Programmable, NonVolatile Integrated Storage) will be used herein to refer generally to integrated devices which store data nonvolatilely but cannot be electrically programmed even once nor electrically erased. Mask-programmed ROM IC's are an example of NP.sub.-- NVIS. Laser-programmed ROM IC's can be another example.
The term `EE.sub.-- NVIS` (Electrically Erasable and reprogrammable, NonVolatile Integrated Storage) will be used herein to refer generally to integrated devices which may be electrically programmed and electrically erased multiple times while storing data nonvolatilely between each programming and subsequent, if any, erasure operation. EPROM devices, EEPROM devices, and FLASH devices all fall under the definition of `EE.sub.-- NVIS` as used herein. UV-erasable PROM IC's do not because they are not electrically erasable.
Returning to the original topic, suppose it is desirable to reconfigure an in-the-field, FPGA system. Suppose further that configuration restoration relies on either a NP.sub.-- NVIS form of CROP device (which is not reprogrammable) or an NE.sub.-- NVIS form of CROP device (which is not electrically erasable). In such a case, a commonly used procedure calls for physical removal of the original NP/NE.sub.-- NVIS CROP device from the system and replacement with a substitute NP/NE.sub.-- NVIS CROP device. The substitute CROP device contains the new FPGA configuration data that will be loaded into the FPGA device during the next restoration cycle.
Even in cases where the original CROP device is a multi-reprogrammable NE.sub.-- NVIS device, meaning that it is a reprogrammable device such as UV-erasable PROM, the original CROP device may still need to be physically removed from the system (or otherwise manually acted on) so as to provide for erasure (e.g., by way of exposure to UV radiation) and for reprogramming of the device (e.g., using voltages higher than can be withstood in-system) before the device is reintroduced back into the end-use system.
The phrase, `CROP rotation` will be used herein to refer to the act of changing the configuration data held within a CROP device irrespective of whether such a change is accomplished with or without replacement or other manual handling of the CROP device.
The phrase, `physical CROP rotation` will be used herein to refer to the act of changing the configuration data held within a CROP device by way of physical substitution or other manual handling. `In-field physical CROP rotation` will refer to physical CROP rotation that is carried out on an end-use system while the latter system is out in the field (as opposed to being brought back to a repair station for rework).
In-field physical CROP rotation is disadvantageous because the in-the-field handling (for replacement or reprogramming of the CROP device) tends to be costly and time-consuming. In some instances the in-system FPGA and/or the remainder of the end-use system needs to be shut-down during the CROP rotation operation. End-users are then deprived of the resources of the in-system FPGA and/or of the remainder of the end-use system during the operation.
It would be beneficial to have an arrangement in which in-system reconfiguration of SRAM-based FPGA's or of other such volatile PLD's can take place without resorting to physical CROP rotation.